Bit Rate Register (Spbcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.3

Bit Rate Register (SPBCR)

SPBCR is a 32-bit register that sets the bit rate.
The settings of this register are reflected both in external address space read mode and SPI operating mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
-
Initial value: 0
R/W: R
Bit:
15
Initial value:
0
R/W:
R/W
Bit Bit Name
31 to 16 ―
15 to 8 SPBR[7:0]
7 to 2 ―
1, 0 BRDV[1:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
SPBR[7:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
All 0 R
All 0 R/W
All 0 R
11 R/W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- - -
0 0 0 0 0
R/W R/W R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Bit Rate
Sets the bit rate. The bit rate is determined by a combination of these bits
with the BRDV[1:0] bits. For details, see Table 17.3, Relationship
between SPBR[7:0] and BRDV[1:0] Settings.
Reserved
These bits are always read as 0. The write value should always be 0.
Bit Rate Frequency Division
Sets the bit rate. The bit rate is determined by a combination of these bits
with the SPBR[7:0] bits. The SPBR value is used to set the base bit rate.
The BRDV value is used to select a division ratio of the base bit rate from
among no division, 2, 4, and 8.
00: Base bit rate
01: Base bit rate divided by 2
10: Base bit rate divided by 4
11: Base bit rate divided by 8
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
- - - BRDV[1:0]
0 0 0 1 1
R R R R/W R/W
17-9