Transmitter Channel 1 Audio Register (Tlca) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Bit Bit Name
0 CBTX
Note 1. When an error bit is detected during DMA transfer, DMA transfer settings must be made again. In this case, the Renesas
SPDIF's module enable bit (either the RME or TME bit) and the DMA enable bit (either the RDE or TDE bit) must be disabled
and the error status must be cleared before making DMA transfer settings again. Then the module enable bit should be set and
DMA transfer can be started again.
23.7.3

Transmitter Channel 1 Audio Register (TLCA)

Bit Bit Name
31 to 24 ―
23 to 0 Audio PCM Data
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Initial
Value R/W Description
0 R Channel 1 and Channel 2 Buffers for Transmitter
Indicates the status of the transmitter audio channel registers. This bit is
cleared by writing to the transmitter audio channel registers. If bit TCBI in
the control register is set this causes an interrupt.
0: Transmitter audio channel registers are full
1: Transmitter audio channel registers are empty
Bit: 31 30 29
- - -
Initial value: - - -
R/W: W W W
Bit: 23 22 21
Initial value: 0 0 0
R/W: W W W
Bit: 15 14 13
Initial value: 0 0 0
R/W: W W W
Bit: 7 6 5
Initial value: 0 0 0
R/W: W W W
Initial
Value R/W Description
― W Reserved
All 0 W Audio PCM Data
LSB aligned PCM encoded audio data.
28 27 26 25 24
- - - - -
- - - - -
W W W W W
20 19 18 17 16
Audio PCM Data
0 0 0 0 0
W W W W W
12 11 10 9 8
Audio PCM Data
0 0 0 0 0
W W W W W
4 3 2 1 0
Audio PCM Data
0 0 0 0 0
W W W W W
23. Renesas SPDIF Interface
23-11