Simultaneous Capture Of Tcnt_1 And Tcnt_2 In Cascade Connection; Notes On Output Waveform Control During Synchronous Counter Clearing In Complementary Pwm Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.22

Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection

When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade
counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and
TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and
TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in
synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-
up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In
this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to
TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred.
10.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing
in Complementary PWM Mode
In complementary PWM mode, when output waveform control during synchronous counter clearing is enabled (WRE in
the TWCR register set to 1), the following problems may occur when condition (1) or condition (2), below, is satisfied.
• Dead time for the PWM output pins may be too short (or nonexistent).
• Active-level output from the PWM negative-phase pins may occur outside the correct active-level output interval
Condition (1): When synchronous clearing occurs in the PWM output dead time interval within initial output
suppression interval (10) (Figure 10.113).
Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or (11) and TGRB_3
≤ TDDR, TGRA_4 ≤ TDDR, or TGRB_4 ≤ TDDR is true (Figure 10.114)
TGRA_3
TGR
TDDR
PWM output
(positive phase)
PWM output
(negative phase)
Figure 10.113 Condition (1) Synchronous Clearing Example
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
(10) (11)
TCNT_3
Tb interval
TCNT_4
0
TDDR
Synchronous clearing
(10)
Tb interval
Shortened dead time
Initial output suppression
Dead time
Note: PWM output is low-active.
10. Multi-Function Timer Pulse Unit 2
(11)
10-152