Data Read Enable Setting Register (Drenr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.8

Data Read Enable Setting Register (DRENR)

DRENR is a 32-bit register that sets the bit size of the command, optional command, address, option data, and read data
in external address space read mode and enables outputting them other than read data.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
CDB[1:0]
Initial value:
0
R/W:
R/W
Bit: 15
DME
Initial value: 0
R/W: R/W
Bit Bit Name
31, 30 CDB[1:0]
29, 28 OCDB[1:0]
27, 26 ―
25, 24 ADB[1:0]
23, 22 ―
21, 20 OPDB[1:0]
19, 18 ―
17, 16 DRDB[1:0]
15 DME
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
OCDB[1:0] - -
0 0 0 0 0
R/W R/W R/W R R
14 13 12 11 10
CDE - OCDE ADE[3:0]
1 0 0 0 1
R/W R R/W R/W R/W
Initial
Value R/W
00 R/W
00 R/W
All 0 R
00 R/W
All 0 R
00 R/W
All 0 R
00 R/W
0 R/W
25 24 23 22 21
ADB[1:0] - - OPDB[1:0]
0 0 0 0 0
R/W R/W R R R/W
9 8 7 6 5
OPDE[3:0]
1 1 0 0 0
R/W R/W R/W R/W R/W
Description
Command Bit Size
Sets the command size in bit units.
00: 1 bit
01: 2 bits
10: 4 bits
11: Setting prohibited
Optional Command Bit Size
Sets the optional command size in bit units.
00: 1 bit
01: 2 bits
10: 4 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value should always be 0.
Address Bit Size
Sets the address size in bit units.
00: 1 bit
01: 2 bits
10: 4 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value should always be 0.
Option Data Bit Size
Sets the option data size in bit units.
00: 1 bit
01: 2 bits
10: 4 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value should always be 0.
Data Read Bit Size
Sets the data read size in bit units.
00: 1 bit
01: 2 bits
10: 4 bits
11: Setting prohibited
Dummy Cycle Enable
Enables insertion of the dummy cycle before the read data.
Note: A setting is prohibited for a transfer starting with a dummy cycle.
0: Dummy cycle insertion disabled
1: Dummy cycle insertion enabled
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- - DRDB[1:0]
0 0 0 0 0
R/W R R R/W R/W
4 3 2 1 0
- - - -
0 0 0 0 0
R/W R R R R
17-15