Spi Multi I/O Bus Controller; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.

SPI Multi I/O Bus Controller

The SPI multi I/O bus controller outputs control signals to the serial flash memory connected to the SPI multi I/O bus
space, thus enabling direct connection of the serial flash memory.
This LSI incorporates an independent SPI multi I/O bus controller channel.
17.1

Features

This module allows the connected serial flash memory to be accessed by directly reading the SPI multi I/O bus space, or
using SPI operating mode to transmit and receive data.
• Serial Flash Memory Interface
Up to two serial flash memories per channel can be connected.
A data bus size of 1 bit, 2 bits, or 4 bits can be selected for one serial flash memory device.
Serial flash memory for DDR transfer can be directly connected (RZ/A1LU only).
• External Address Space Read Mode
A maximum of 8-Gbyte address space is supported (when two serial flash memories are connected)
The SPBSSL pin can be automatically controlled through access address monitoring
Efficient data reception due to built-in read cache (64-bit line × 16 entries)
• SPI Operating Mode
Desired read/write access to serial flash memory possible
• Bit rate
SPBCLK is generated by frequency division of Bφ by internal baud rate generator
SPBCLK frequency division ratio can be set from 2 to 4080
• SPBSSL Pin Control
Delay from SPBSSL signal assertion to SPBCLK operation (clock delay) can be set
Range: 1 to 8 SPBCLK cycles (set in SPBCLK-cycle units)
Delay from SPBCLK stop to SPBSSL output negation (SPBSSL negation delay) can be set
Range: 1.5 to 8.5 SPBCLK cycles (set in SPBCLK-cycle units)
SPBSSL output assertion wait before next access (next access delay) can be set
Range: 1 to 8 SPBCLK cycles (set in SPBCLK-cycle units)
SPBSSL polarity can be changed
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
17. SPI Multi I/O Bus Controller
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