Serial Data Transmission (Except In Block Transfer Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.6.6

Serial Data Transmission (Except in Block Transfer Mode)

Serial data transmission in smart card interface mode (except in block transfer mode), in that an error signal is sampled
and data can be re-transmitted, is different from that in normal serial communications interface mode. Figure 15.30
shows the data retransfer operation during transmission.
1. When an error signal from the receiver end is sampled after one-frame data has been transmitted, the ERS flag in
SSR is set to 1. If the RIE bit in SCR is 1 at this time, an ERI interrupt request is generated. Clear the ERS flag in
SSR to 0 before the next parity bit is sampled.
2. For a frame in which an error signal is received, the TEND flag in SSR is not set. Data is retransferred from TDR to
TSR allowing automatic data retransmission.
3. If no error signal is returned from the receiver, the ERS flag in SSR is not set to 1.
4. In this case, the SCI judges that transmission of one-frame data (including retransfer) has been completed, and the
TEND flag is set. If the TIE bit in SCR is 1 at this time, a TXI interrupt request is generated. Writing transmit data
to TDR starts transmission of the next data.
Figure 15.32 shows a sample flowchart of serial transmission. All the processing steps are automatically performed
using a TXI interrupt request to activate the DMAC.
When the TEND flag in SSR is set to 1 in transmission, if the TIE bit in SCR is 1, a TXI interrupt request is generated.
The DMAC is activated by a TXI interrupt request if the TXI interrupt request is specified as a source of DMAC
activation beforehand, allowing transfer of transmit data. The TEND flag in SSR is automatically cleared to 0 when the
DMAC transfers the data.
If an error occurs, the SCI automatically re-transmits the same data. During this retransmission, the TEND flag in SSR is
kept to 0 and the DMAC is not activated. Therefore, the SCI and DMAC automatically transmit the specified number of
bytes, including retransmission in the case of error occurrence. However, since the ERS flag in SSR is not automatically
cleared, set the RIE bit in SCR to 1 beforehand to enable an ERI interrupt request to be generated at error occurrence, and
clear the ERS flag in SSR to 0.
When transmitting/receiving data using the DMAC, be sure to make settings to enable the DMAC before making SCI
settings.
For DMAC settings, see section 9, Direct Memory Access Controller.
Ds D0 D1 D2
TXI interrupt signal
SSR.FER flag/
SSR.ERS flag
Figure 15.30 Data Retransfer Operation in Transmission Mode
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
n-th transfer frame
D3 D4 D5 D6 D7 Dp DE
[2]
[1]
15. Serial Communications Interface
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1)-th transfer
frame
(DE)
Ds D0 D1 D2 D3 D4
[4]
[3]
15-52