Bit Rate Register (Scbrr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.8

Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that is used with the CKS[1:0] bits in the serial mode register (SCSMR) and the BGDM and
ABCS bits in the serial extension mode register (SCEMR) to determine the serial transmit/receive bit rate.
The CPU can always read from and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. Each channel
has independent baud rate generator control, so different values can be set in eight channels.
The SCBRR setting is calculated as follows:
• Asynchronous mode:
When baud rate generator operates in normal mode (when the BGDM bit of SCEMR is 0):
P1φ
N =
64 × 2
2n-1
P1φ
N =
32 × 2
2n-1
When baud rate generator operates in double speed mode (when the BGDM bit of
SCEMR is 1):
P1φ
N =
32 × 2
2n-1
P1φ
N =
16 × 2
2n-1
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
Initial value: 1 1
R/W: R/W R/W
× 10 − 1 (Operation on a base clock with a frequency of 16 times
6
× B
the bit rate)
× 10 − 1 (Operation on a base clock with a frequency of 8 times
6
× B
the bit rate)
× 10 − 1 (Operation on a base clock with a frequency of 16 times
6
× B
the bit rate)
× 10 − 1 (Operation on a base clock with a frequency of 8 times
6
× B
the bit rate)
14. Serial Communication Interface with FIFO
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W
0
1
R/W
14-15