Peripheral Buses - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.2.3

Peripheral Buses

Table 5.2 is a list of the peripheral buses connected to the north main bus.
Table 5.2 List of Peripheral Buses
Item
Peripheral bus 1
Bus clock frequency
Bus width
Connected peripheral modules
Peripheral bus 2
Bus clock frequency
Bus width
Connected peripheral modules
Peripheral bus 3
Bus clock frequency
Bus width
Connected peripheral modules
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Description
P0φ
32 bits
Multi-function timer pulse unit 2
Realtime clock
Video display controller 5
P0φ
32 bits
Clock pulse generator
Interrupt controller
Direct memory access controller
OS timer channels 0 and 1
2
I C bus interface channels 0 to 3
IEBus controller (RZ/A1L only)
LIN interface (RZ/A1L only)
General I/O ports
P1φ
32 bits
CAN interface
Media local bus (RZ/A1L only)
SD host interface channels 0 and 1
MMC host interface
5. LSI Internal Bus
5-3