Usage Notes; Notes On Transfer To Read Data In Spi Operating Mode; Notes On Starting Transfer From The Spbssl Retained State In Spi Operating Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.6

Usage Notes

17.6.1

Notes on Transfer to Read Data in SPI Operating Mode

If the setting for the bit mode is for division by two or more in SPI operating mode, take note of the following points for
caution when setting the SPI mode enable setting register (SMENR) to enable transfer only for reading data.
"Transfer only for reading data" indicates transfer to read data while the CDE, OCDE, ADE[3:0], and OPDE[3:0] bits in
SMENR are all 0.
(1) Transfer to read data while the signal on the SPBSSL pin is de-asserted
Set the SMENR.SPIDE[3:0] bits to 1100 or 1111 when transfer only for reading data is to proceed.
Transfer will not proceed normally if the setting of the SMENR.SPIDE[3:0] bits is 1000.
(2) Transfer to read data while the signal on the SPBSSL pin is asserted
When transfer only for reading data is to proceed, set the SMENR.SPIDE[3:0] bits to 1100 or 1111, or end the
immediately preceding transfer with reading data.
When the immediately preceding transfer is of a command, optional command, address, or option data, or is transfer for
writing data, the subsequent transfer only for reading data will not proceed normally if the setting of the
SMENR.SPIDE[3:0] bits is 1000.
17.6.2 Notes on Starting Transfer from the SPBSSL Retained State in SPI Operating
Mode
Be sure to set the SPIWE bit in the SMCR register to 1 when the transfer of a command, optional command, address, or
option data is started while the SPBSSL pin is being asserted in SPI operating mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
17. SPI Multi I/O Bus Controller
17-53