Common Control Register (Cmncr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.4.1

Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area.
Bit:
31
-
Initial value: 0
R/W:
R
Bit: 15
-
Initial value: 0
R/W:
R
Bit Bit Name
31 to 29 ―
28 TL0
27 to 25 ―
24 AL0
23 to 13 ―
12 ―
11 ―
10, 9 DPRTY[1:0]
8 to 5 ―
4, 3 ―
2 ―
1 HIZMEM
0 HIZCNT*
Note: * For High-Z control of CKIO, see section 6, Clock Pulse Generator.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - TL0 - -
0 0 0 0 0
R R R/W R R
14 13 12 11 10
- - - - DPRTY[1:0]
0 0 1 0 0
R R R R R/W
Initial
Value R/W
All 0 R
0 R/W
All 0 R
0 R/W
All 0 R
1 R
0 R
00 R/W
All 0 R
All 1 R
0 R
0 R/W
0 R/W
25 24 23 22 21
- AL0 - - -
0 0 0 0 0
R R/W R R R
9 8 7 6 5
- - - -
0 0 0 0 0
R/W R R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Transfer End Level
Specifies the TEND0 signal output is high active or low active.
0: Low-active output from TEND0
1: High-active output from TEND0
Reserved
These bits are always read as 0. The write value should always be 0.
Specifies the DACK0 (acknowledge) signal output is high active or low
active.
0: Low-active output from DACK0
1: High-active output from DACK0
Reserved
These bits are always read as 0. The write value should always be 0.
Reserved
This bit is always read as 1. The write value should always be 1.
Reserved
This bit is always read as 0. The write value should always be 0.
DMA Burst Transfer Priority
Specify the priority for a refresh request during DMA burst transfer.
0*: Accepts a refresh request during DMA burst transfer.
10: Does not accept a refresh request during DMA burst transfer.
11: Reserved (setting prohibited)
Reserved
These bits are always read as 0. The write value should always be 0.
Reserved
These bits are always read as 1. The write value should always be 1.
Reserved
This bit is always read as 0. The write value should always be 0.
High-Z Memory Control
Specifies the pin state in software standby mode or deep standby mode
for A25 to A0, BS, CSn, RD/WR, WEn/DQMxx/AH, and RD.
0: High impedance in software standby mode or deep standby mode.
1: Driven in software standby mode or deep standby mode
High-Z Control
Specifies the state in software standby mode or deep standby mode for
CKE, RAS, and CAS.
0: High impedance in software standby mode or deep standby mode for
CKE, RAS, and CAS.
1: Driven in software standby mode or deep standby mode for CKE, RAS,
and CAS.
8. Bus State Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
HIZ HIZ
- - -
MEM CNT*
1 1 0 0 0
R R R R/W R/W
8-7