Rscan0Cftists - Transmit/Receive Fifo Buffer Transmit Interrupt Flag Status Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.42 RSCAN0CFTISTS — Transmit/receive FIFO buffer Transmit Interrupt Flag
Status Register
Access: Can be read in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 024C
Initial value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.56
Bit Position
31 to 6
5
4
3
2
1
0
The RSCAN0CFTISTS register is cleared to 0000 0000
CFkTXIF Flag (k = 0 to 5)
The CFkTXIF flag is set to 1 when the CFTXIF flag in the RSCAN0CFSTSk register is set to 1 (a
transmit/receive FIFO transmit interrupt request is present). When the CFTXIF flag is cleared to 0, the
CFkTXIF flag is cleared to 0.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RSCAN0CFTISTS register contents
Bit Name Function
Reserved These bits are always read as 0.
CF5TXIF Transmit/Receive FIFO Buffer Transmit Interrupt Request Status Flag
CF4TXIF
CF3TXIF (k = 0 to 5)
CF2TXIF
CF1TXIF
CF0TXIF
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — — —
0 0 0 0
R R R R
0: No transmit/receive FIFO buffer k transmit interrupt request is present.
1: A transmit/receive FIFO buffer k transmit interrupt request is present.
in global reset mode.
H
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
CF5TXI CF4TXI CF3TXI CF2TXI
F F F F
0 0 0 0
R R R R
17 16
— —
0 0
R R
1 0
CF1TXI CF0TXI
F F
0 0
R R
21-86