Rscan0Tmiecy - Transmit Buffer Interrupt Enable Configuration Register Y (Y = 0) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.49 RSCAN0TMIECy — Transmit Buffer Interrupt Enable Configuration Register y
(y = 0)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0390
Initial value: 0000 0000
H
Bit 31 30 29
Initial value 0 0 0
R/W R/W R/W R/W
Bit 15 14 13
0 0 0
Initial value
R/W R/W R/W R/W
Table 21.67
Bit Position
31 to 16
15 to 0
TMIEp Bits (p = 0 to 31)
When any of these bits is set to 1 and the corresponding transmission has been completed, a transmit
buffer interrupt request is generated.
Modify these bits when the TMTRM flag in the corresponding RSCAN0TMSTSp register is 0 (no
transmit request is present).
Write 0 to bits corresponding to transmit buffers linked to transmit/receive FIFO buffers or transmit
buffers allocated to the transmit queue.
Table 21.68 shows the bit assignment.
Table 21.68
0
1
.
.
15
16
.
.
30
31
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (y * 0004 )
H H
28 27 26 25
TMIEp (p = y × 32 + 31 to y × 32 + 16 (y = 0))
0 0 0 0
R/W R/W R/W R/W
12 11 10 9
TMIEp (p = y × 32 + 15 to y × 32 + 0 (y = 0))
0 0 0 0
R/W R/W R/W R/W
RSCAN0TMIECy register contents
Bit Name Function
Transmit Buffer Interrupt Enable Bit p (p = y × 32 + 31 to y × 32 + 16)
TMIEp
0: Transmit buffer interrupt is disabled
1: Transmit buffer interrupt is enabled
TMIEp Transmit Buffer Interrupt Enable Bit p (p = y × 32 + 15 to y × 32 + 0)
0: Transmit buffer interrupt is disabled.
1: Transmit buffer interrupt is enabled.
TMIEp Bit Assignment
Bit Channel
0
0
.
.
0
1
.
.
1
1
24 23 22 21
0 0 0 0
R/W R/W R/W R/W
8 7 6 5
0 0 0 0
R/W R/W R/W R/W
Transmit Buffer Number
0
1
.
.
15
0
.
.
14
15
21. CAN Interface
20 19 18 17
0 0 0 0
R/W R/W R/W R/W
4 3 2 1
0 0 0 0
R/W R/W R/W R/W
16
0
R/W
0
0
R/W
21-95