Timeout Cycle Constant Register (Toscorn) (N = 0 To 5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.4.8

Timeout Cycle Constant Register (TOSCORn) (n = 0 to 5)

TOSCORn is a 16-bit register the value of which is effective when the WM bit in the CSn space wait control register
(CSnWCR) is 0 and the corresponding bit in the timeout enable register (TOENR) is 1. When the number of cycles of
waiting due to the signal on the eternal wait input pin matches the setting of TOSCORn, external wait input is disabled to
end the cycle of access, the timeout status flag for the corresponding space in the timeout status register (TOSTR) is set,
and a timeout detection interrupt request is generated. The timeout detection interrupt request is retained until the
corresponding bit in TOENR is set to 0 or 0 is written to the timeout status flag for the corresponding space. Note that
timeout detection is enabled even while the timeout status flag for the corresponding space in TOSTR is 1, and external
wait input is disabled in response to a further timeout.
Bit: 31
-
Initial value: 0
R/W:
R
Bit: 15
Initial value: 0
R/W: R/W
Bit Bit Name
31 to 16 ―
15 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
All 0 R
All 0 R/W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
0 0 0 0 0
R/W R/W R/W R/W R/W
Description
Reserved
These bits are always read as 0.
16-Bit Register
H'0000: 65536 cycles
H'0001: 1 cycle
:
H'FFFF: 65535 cycles
8. Bus State Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
8-31