Slave Select Negation Delay Register (Sslnd) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.11

Slave Select Negation Delay Register (SSLND)

SSLND sets a period (SSL negation delay) from the transmission of a final RSPCK edge to the negation of the SSL
signal during a serial transfer by this module in master mode. If the contents of SSLND are changed while the MSTR and
SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent
operation cannot be guaranteed.
When using this module in slave mode, set B'000 to SLNDL2 to SLNDL0.
Bit Bit Name
7 to 3 ―
2 SLNDL2
1 SLNDL1
0 SLNDL0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
⎯ ⎯ ⎯
Initial value: 0 0 0
R/W: R R R
Initial Value R/W Function
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R/W SSL Negation Delay Setting
0 R/W These bits set an SSL negation delay when the SLNDEN bit in SPCMD is
0 R/W 1.
The relationship between the setting of SLNDL2 to SLNDL0 and the SSL
negation delay value is shown below.
000: 1 RSPCK
001: 2 RSPCK
010: 3 RSPCK
011: 4 RSPCK
100: 5 RSPCK
101: 6 RSPCK
110: 7 RSPCK
111: 8 RSPCK
16. Renesas Serial Peripheral Interface
4 3 2 1 0
SLN SLN SLN
⎯ ⎯
DL2 DL1 DL0
0 0 0 0 0
R R R/W R/W R/W
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