Operation; Overview - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.4

Operation

14.4.1

Overview

For serial communication, this module has an asynchronous mode in which characters are synchronized individually, and
a clock synchronous mode in which communication is synchronized with clock pulses.
This module has a 16-stage FIFO buffer for both transmission and reception, reducing the overhead of the CPU, and
enabling continuous high-speed communication. Furthermore, channels 0, 1, and 2 have RTS and CTS signals to be used
as modem control signals.
The transmission/reception format is selected in the serial mode register (SCSMR), as shown in Table 14.9. The clock
source is selected by the combination of the C/A bit in SCSMR and the CKE[1:0] bits in the serial control register
(SCSCR), as shown in Table 14.10.
(1) Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes
the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data
ready, and breaks.
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the clock source.
—
When an internal clock is selected, this module operates using the clock of on-chip baud rate generator.
—
When an external clock is selected, the external clock input must have a frequency 16 or 8 times the bit rate.
(The on-chip baud rate generator is not used.)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14. Serial Communication Interface with FIFO
14-26