Register Descriptions; Control Register (Ctrl) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.7

Register Descriptions

Legend:
Initial Value: Register value after reset
⎯:
Undefined value
R/W: Readable/writable register. The write value can be read.
R: Read only register. The write value should always be 0.
R/WC0: Readable/writable register. Writing 0 initializes the bit, but writing 1 is ignored.
R/WC1: Readable/writable register. Writing 1 initializes the bit, but writing 0 is ignored.
W: Write only register. Reading is prohibited. If this bit is reserved, the write value should always be 0.
—/W: Write only, Read value undefined
23.7.1

Control Register (CTRL)

Bit Bit Name
31 to 29 ―
28 CKS
27 ―
26 PB
25, 24 RASS
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 31 30 29
- - -
Initial value: 0 0 0
R/W: R R R
Bit: 23 22 21
TASS RDE
Initial value: 0 0 0
R/W: R/W R/W R/W
Bit: 15 14 13
REIE TEIE UBOI UBUI CREI
Initial value: 0 0 0
R/W: R/W R/W R/W
Bit: 7 6 5
ABOI ABUI RUII
Initial value: 0 0 0
R/W: R/W R/W R/W
Initial
Value R/W Description
All 0 R Reserved
0 R/W Oversampling clock select
Selects oversampling clock supply source.
0: AUDIO_X1
1: AUDIO CLK
0 R Reserved
0 R/W Pass Back
Passes transmitter SPDIF output into SPDIF receiver in SPDIF module.
0: Pass Back disabled
1: Pass Back enabled
All 0 R/W Receiver Audio Sample Bit Size
These bits Indicate the receiver audio sample bit size (16, 20, or 24 bits),
for data alignment purposes.
00: 16-bit sample
01: 20-bit sample
10: 24-bit sample
11: Reserved
28 27 26 25 24
CKS - PB RASS
0 0 0 0 0
R/W R R/W R/W R/W
20 19 18 17 16
TDE NCSI AOS RME TME
0 0 0 0 0
R/W R/W R/W R/W R/W
12 11 10 9 8
PAEI PREI CSEI
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
TUII RCSI RCBI TCSI TCBI
0 0 0 0 0
R/W R/W R/W R/W R/W
23. Renesas SPDIF Interface
23-6