Axi Bus Control Register 6 (Axibusctl6) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.5

AXI Bus Control Register 6 (AXIBUSCTL6)

This register controls the cache operation for video display controller 5.
Bit:
31
—
Initial value: 0
R/W:
R
Bit:
15
—
Initial value:
0
R/W:
R
Bit Bit Name
31 to 28 —
27 to 24 VDC501AR
CACHE
[3:0]
23 to 20 —
19 to 16 VDC501AW
CACHE
[3:0]
15 to 12 —
11 to 8 VDC502AR
CACHE
[3:0]
7 to 0 —
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
— — — VDC501ARCACHE[3:0]
0 0 0 0
R R R R/W R/W
14 13 12 11 10
— — — VDC502ARCACHE[3:0]
0 0 0 0
R R R R/W R/W
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0000 R/W ARCACHE[3:0] Signals for Video Display Controller 5 IV3-BUS
These bits specify the system cache operation when the IV3-BUS of video display
controller 5 performs read access. The values of these bits are used as the
ARCACHE[3:0] signals for the IV3-BUS of video display controller 5. Modify the
values of these bits only while video display controller 5 does not use the internal
bus.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0000 R/W AWCACHE[3:0] Signals for Video Display Controller 5 IV1-BUS
These bits specify the system cache operation when the IV1-BUS of video display
controller 5 performs write access. The values of these bits are used as the
AWCACHE[3:0] signals for the IV1-BUS of video display controller 5. Modify the
values of these bits only while video display controller 5 does not use the internal
bus.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0000 R/W ARCACHE[3:0] Signals for Video Display Controller 5 IV5-BUS
These bits specify the system cache operation when the IV5-BUS of video display
controller 5 performs read access. The values of these bits are used as the
ARCACHE[3:0] signals for the IV5-BUS of video display controller 5. Modify the
values of these bits only while video display controller 5 does not use the internal
bus.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22
— —
0 0 0 0 0
R/W R/W R R
9 8 7 6
— —
0 0 0 0 0
R/W R/W R R
5. LSI Internal Bus
21 20 19 18 17
— — VDC501AWCACHE[3:0]
0 0 0 0 0
R R R/W R/W R/W
5 4 3 2 1
— — —
— —
0 0 0 0 0
R R R R R
16
0
R/W
0
—
0
R
5-18