Control Register 3 (Rcr3); Control Register 5 (Rcr5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
13.3.18

Control Register 3 (RCR3)

When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among RSECAR/RMINAR/
RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those
with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1.
Bit Bit Name
7 ENB
—
6 to 0
13.3.19

Control Register 5 (RCR5)

When the RCKSEL[1:0] bits in RCR5 are set to 00 and 01, the RTC_X1 clock pulses (32.768 kHz) and the EXTAL
clock pulses are used for clock counting, respectively.
Bit Bit Name
—
7 to 2
1, 0 RCKSEL[1:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
BIt: 7 6
ENB -
Initial value: 0
Undefined
R/W: R/W R
Initial
Value R/W Description
Undefined R/W When this bit is set to 1, comparison of the year alarm register (RYRAR) and the
year counter (RYRCNT) is performed.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
Bit:
7 6
- -
Initial value:
0 0
R/W:
R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
Undefined R/W Operation clock select
Operation clock can be selected from RTC_X1 and EXTAL.
The setting of these bits should not be switched during operation.
00: Selects RTC_X1 (32.768 kHz).
01: Selects EXTAL.
10: Reserved.
11: Setting prohibited.
5 4 3 2 1
- - - - -
0 0 0 0 0
R R R R R
5 4 3 2 1
- - - - RCKSEL[1:0]
0 0 0 0
Undefined Undefined
R R R R R/W
13. Realtime Clock
0
-
0
R
0
R/W
13-14