Common Status Register (Cmnsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.18

Common Status Register (CMNSR)

CMNSR is a 32-bit register that holds flags indicating the operating state.
The settings of this register are reflected both in external address space read mode and SPI operating mode.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 2 ―
1 SSLF
0 TEND
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R
1 R
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- - - - -
0 0 0 0 0
R R R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
SPBSSL Pin Monitor
0: SPBSSL pin is negated
1: SPBSSL pin is asserted
Transfer End Flag
Indicates whether the data transfer has ended.
0: Indicates that data transfer is in progress
1: Indicates that data transfer has ended
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
- - - SSLF TEND
0 0 0 0 1
R R R R R
17-24