Timer Output Control Register 2 (Tocr2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.18

Timer Output Control Register 2 (TOCR2)

TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary
PWM mode and reset-synchronized PWM mode.
Bit Bit Name
7, 6 BF[1:0]
5 OLS3N
4 OLS3P
3 OLS2N
2 OLS2P
1 OLS1N
0 OLS1P
Note: Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid.
*
If the dead-time is not generated, the negative-phase output will be the exact inverse of the positive-phase output.
Furthermore, set OLSiP and OLSiN (i = 1, 2, 3) to the same value.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
Initial value:
0 0
R/W: R/W R/W
Initial
value R/W Description
00 R/W TOLBR Buffer Transfer Timing Select
These bits select the timing for transferring data from TOLBR to TOCR2.
For details, see Table 10.30.
0 R/W Output Level Select 3N*
This bit selects the output level on TIOC4D in reset-synchronized PWM mode/
complementary PWM mode. See Table 10.31.
0 R/W Output Level Select 3P*
This bit selects the output level on TIOC4B in reset-synchronized PWM mode/
complementary PWM mode. See Table 10.32.
0 R/W Output Level Select 2N*
This bit selects the output level on TIOC4C in reset-synchronized PWM mode/
complementary PWM mode. See Table 10.33.
0 R/W Output Level Select 2P*
This bit selects the output level on TIOC4A in reset-synchronized PWM mode/
complementary PWM mode. See Table 10.34.
0 R/W Output Level Select 1N*
This bit selects the output level on TIOC3D in reset-synchronized PWM mode/
complementary PWM mode. See Table 10.35.
0 R/W Output Level Select 1P*
This bit selects the output level on TIOC3B in reset-synchronized PWM mode/
complementary PWM mode. See Table 10.36.
5 4 3 2 1
0 0 0 0 0
R/W R/W R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
0
R/W
10-48