Area Overview; Address Map - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.3

Area Overview

8.3.1

Address Map

In the architecture, this LSI has a 32-bit address space, which is divided into external memory spaces (SPI multi I/O bus
space, large-capacity on-chip RAM, hold on-chip RAM, on-chip peripheral modules, and reserved areas) according to
the upper bits of the address.
See section 5, LSI Internal Bus (including Secondary Cache) for how to enable or disable caching for the CS0 to CS5
external address spaces.
The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the
external address space is listed below.
Table 8.2 Address Map
Internal Address
H'00000000 to H'03FFFFFF
H'04000000 to H'07FFFFFF
H'08000000 to H'0BFFFFFF
H'0C000000 to H'0FFFFFFF
H'10000000 to H'13FFFFFF
H'14000000 to H'17FFFFFF
H'18000000 to H'3FFFFFFF
H'40000000 to H'407FFFFF
H'40800000 to H'43FFFFFF
H'44000000 to H'47FFFFFF
H'48000000 to H'4BFFFFFF
H'4C000000 to H'4FFFFFFF
H'50000000 to H'53FFFFFF
H'54000000 to H'57FFFFFF
H'58000000 to H'FFFFFFFF
Note 1. For the large-capacity on-chip RAM space and hold on-chip RAM space, access the addresses shown in section 40, On-Chip
RAM. For the on-chip peripheral module space, access the addresses shown in section 46, List of Registers. Do not access
addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed.
Note 2. For details, see section 5, LSI Internal Bus.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Space Memory to be Connected
CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or
synchronous)
CS1 Normal space, SRAM with byte selection
CS2 Normal space, SRAM with byte selection, SDRAM
CS3 Normal space, SRAM with byte selection, SDRAM
CS4 Normal space, SRAM with byte selection,
burst ROM (asynchronous)
CS5 Normal space, SRAM with byte selection, MPX-I/O
Other SPI multi I/O bus space, large-capacity on-chip RAM, hold on-chip RAM, on-
chip peripheral modules, reserved area*
CS0 mirror Access from the north main bus is not possible, but access from the south
main bus is possible.
CS0 mirror Normal space, SRAM with byte selection, burst ROM (asynchronous or
synchronous)
CS1 mirror Normal space, SRAM with byte selection
CS2 mirror Normal space, SRAM with byte selection, SDRAM
CS3 mirror Normal space, SRAM with byte selection, SDRAM
CS4 mirror Normal space, SRAM with byte selection, burst ROM (asynchronous)
CS5 mirror Normal space, SRAM with byte selection, MPX-I/O
Other SPI multi I/O bus space (mirror), large-capacity on-chip RAM (mirror), hold on-
chip RAM (mirror), on-chip peripheral modules, reserved area*
1
*2
8. Bus State Controller
1
8-4