Initialization (Smart Card Interface Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Internal base clock
Receive data (RXDn)
Synchronization sampling
timing
Data sampling timing
Figure 15.29 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate)
15.6.5

Initialization (Smart Card Interface Mode)

Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary
before switching from transmission to reception and vice versa.
1. Write the initial value "00h" to the SCR.
2. Make general-purpose I/O port settings to enable input and output functions as required for TXDn, RXDn, and
SCKn pins.
3. Set the error flags ORER, ERS, and PER in SSR to 0.
4. Set bits GM, BLK, PM, BCP[1:0], and CKS[1:0] in SMR and the BCP2 bit in SCMR appropriately. Also set the PE
bit in SMR to 1.
5. Set bits SDIR, SINV, and SMIF in SCMR appropriately. Then, the TXDn and RXDn pins are placed in the high
impedance state.
6. Set the value corresponding to the bit rate in BRR.
7. Set the CKE[1:0] bits in SCR appropriately, and set bits TIE, RIE, TE, RE, and TEIE in SCR to 0 at the same time.
When the CKE[1:0] bit in SCR is set to 1, the SCKn pin is allowed to output clock pulses.
8. Set the TIE, RIE, TE, and RE bits in SCR to 1. Setting the TE and RE bits to 1 simultaneously is prohibited except
for self-diagnosis.
To change reception mode to transmission mode, first check that reception has completed, and then initialize the SCI. At
the end of initialization, set SCR.TE = 1 and SCR.RE = 0. Reception completion can be verified by reading the RXI
request, ORER, or PER flag in SSR.
To change transmission mode to reception mode, first check that transmission has completed, and then initialize the SCI.
At the end of initialization, set SCR.TE = 0 and SCR.RE = 1. Transmission completion can be verified by reading the TEND
flag in SSR.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
372 clock cycles
186 clock cycles
0 185 371
Start bit
15. Serial Communications Interface
372 clock cycles
186 clock cycles
0 185
D0
371 0
D1
15-51