Notes On Board Design; Note On Using A Pll Oscillation Circuit - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.8

Notes on Board Design

6.8.1

Note on Using a PLL Oscillation Circuit

In the PLLVcc connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible
and pattern width must be as wide as possible to reduce inductive interferences.
Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive
interference at the other power supply pins. To prevent such malfunction, the analog power supply pins and the digital
power supply pins Vcc and PVcc should not supply the same resources on the board if at all possible.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
6. Clock Pulse Generator
6-13