Riicnser - I²C Bus Status Enable Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.7 RIICnSER — I²C Bus Status Enable Register
Access: RIICnSER is a 32-bit readable/writable register.
RIICnSERL and RIICnSERH are 16-bit readable/writable registers.
RIICnSERLL, RIICnSERLH, RRIICnSERHL, and RIICnSERHH are 8-bit readable/writable registers.
Address: RIICnSER: <RIICn_base> + 0018
RIICnSERL: <RIICn_base> + 0018
RIICnSERLL: <RIICn_base> + 0018
RIICnSERHH: <RIICn_base> + 001B
Initial Value: 0000 0009
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.12
Bit Position
31 to 8
7
6
5
4
3
2
1
0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnSERH: <RIICn_base> + 001A
H
, RIICnSERLH: <RIICn_base> + 0019
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnSER register contents
Bit Name Function
― Reserved
These bits are read as 0. The write value should be 0.
HOAE Host Address Enable
0: Host address detection is disabled.
1: Host address detection is enabled.
— Reserved
This bit is read as 0. The write value should be 0.
DIDE Device-ID Address Detection Enable
0: Device-ID address detection is disabled.
1: Device-ID address detection is enabled.
— Reserved
This bit is read as 0. The write value should be 0.
GCE General Call Address Enable
0: General call address detection is disabled.
1: General call address detection is enabled.
SAR2 Slave Address Register 2 Enable
0: Slave address in RIICnSAR2 is disabled.
1: Slave address in RIICnSAR2 is enabled.
SAR1 Slave Address Register 1 Enable
0: Slave address in RIICnSAR1 is disabled.
1: Slave address in RIICnSAR1 is enabled.
SAR0 Slave Address Register 0 Enable
0: Slave address in RIICnSAR0 is disabled.
1: Slave address in RIICnSAR0 is enabled.
H
, RIICnSERHL: <RIICn_base> + 001A
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — HOAE —
0 0 0 0
R R R/W R
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
DIDE — GCE SAR2
0 0 1 0
R/W R R/W R/W
,
H
17 16
— —
0 0
R R
1 0
SAR1 SAR0
0 1
R/W R/W
18-23