Input/Output Pins - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.2

Input/Output Pins

Table 8.1 shows the pin configuration.
Table 8.1 Pin Configuration
Name
A25 to A0
D31 to D0
BS
CS0 to CS5
RD/WR
RD
WE3/DQMUU/AH
WE2/DQMUL
WE1/DQMLU
WE0/DQMLL
RAS
CAS
CKE
WAIT
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
I/O Function
Output Address bus
I/O Data bus
Output Bus cycle start
Output Chip select
Output Read/write
Connects to WE pins when SDRAM or SRAM with byte selection is connected.
Output Read pulse signal (read data output enable signal)
Output Indicates that D31 to D24 are being written to.
Connected to the byte select signal when a SRAM with byte selection is
connected.
Functions as the select signals for D31 to D24 when SDRAM is connected.
Functions as the address hold signal when the MPX-I/O is used.
Output Indicates that D23 to D16 are being written to.
Connected to the byte select signal when a SRAM with byte selection is
connected.
Functions as the select signals for D23 to D16 when SDRAM is connected.
Output Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a SRAM with byte selection is
connected.
Functions as the select signals for D15 to D8 when SDRAM is connected.
Output Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a SRAM with byte selection is
connected.
Functions as the select signals for D7 to D0 when SDRAM is connected.
Output Connects to RAS pin when SDRAM is connected.
Output Connects to CAS pin when SDRAM is connected.
Output Connects to CKE pin when SDRAM is connected.
Input External wait input
8. Bus State Controller
8-3