Fc Control Register (Ssifccr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.10

FC Control Register (SSIFCCR)

SSIFCCR is a 32-bit readable/writable register that controls frequency change detection.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value:
0
R/W: R
Bit Bit Name
31 to 17 ―
16 FIEN
15 to 1 ―
0 FCEN
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/W
All 0 R
0 R/W
25 24 23 22 21
- - - -
0 0 0 0
R R R R R
9 8 7 6
- - - -
0 0 0 0
R R R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Frequency Change Detection Interrupt Enable
0: Disables a frequency change detection interrupt.
1: Enables a frequency change detection interrupt.
Reserved
These bits are always read as 0. The write value should always be 0.
Frequency Change Detection Enable
When this bit is set to 1, counting up of cycles of peripheral clock 1 (P1φ)
starts at the beginning of the next SSIWS cycle. On the start of each SSIWS
cycle, the current counted value is moved to the VALUE bits in the FC Status
Register (SSIFCSR). The counter is then cleared to 0 and counting up is
resumed. When this bit is set to 0, the counter is cleared to 0 and counting
up is stopped.
0: Disables frequency change detection.
1: Enables frequency change detection.
Note: Set this bit to 1 after setting the desired values in SSICR, SSIFCMR,
and SSITDMR.
19. Serial Sound Interface
20 19 18 17
- - - - -
0 0 0 0 0
R R R R
5 4 3 2 1
- - - - -
0 0 0 0 0
R R R R
16
FIEN
0
R/W
0
FCEN
0
R/W
19-19