Transmit Shift Register (Sctsr); Transmit Fifo Data Register (Scftdr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.3

Transmit Shift Register (SCTSR)

SCTSR transmits serial data. Transmit data is loaded from the transmit FIFO data register (SCFTDR) into SCTSR, then
the data is transmitted serially from the TxD pin, LSB (bit 0) first. After one data byte has been transmitted, the next
transmit data is automatically loaded from SCFTDR into SCTSR and transmission is started again.
The CPU cannot read from or write to SCTSR directly.
14.3.4

Transmit FIFO Data Register (SCFTDR)

SCFTDR is a 16-stage FIFO register that stores data for serial transmission. When the transmit shift register (SCTSR)
empty is detected, transmit data written in the SCFTDR is moved to SCTSR and serial transmission is started.
Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can write to
SCFTDR at all times.
When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of next data is attempted, the
data is ignored.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
Initial value: - - -
R/W: - - -
Bit: 7 6 5
Initial value: - - -
R/W: W W W
14. Serial Communication Interface with FIFO
4 3 2 1 0
- - - - -
- - - - -
4 3 2 1 0
- - - - -
W W W W W
14-6