Registers; Registers Overview - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
11.2

Registers

The OS timer is controlled and operated by the following registers.
11.2.1

Registers Overview

The list of OSTMn (n = 0, 1) registers and the memory addresses are as follows.
For the base addresses, see the Table 11.2.
For the actual addresses, the offset values indicated in the following table are added to the base
addresses.
Register
Name
OSTMnCMP
OSTMnCNT
OSTMnTE
OSTMnTS
OSTMnTT
OSTMnCTL
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Function
OSTM compare register
OSTM counter register
OSTM count enable status register R
OSTM count start trigger register
OSTM count stop trigger register
OSTM control register
Access Unit
(bit)
R/W Reset Value 8 16
R/W 0000 0000 — —
H
R FFFF FFFF — —
H
00 √ —
H
W 00 √ —
H
W 00 √ —
H
R/W 00 √ —
H
11. OS Timer
32 Address
√ <OSTMn_base> + 00
H
√ <OSTMn_base> + 04
H
— <OSTMn_base> + 10
H
— <OSTMn_base> + 14
H
— <OSTMn_base> + 18
H
— <OSTMn_base> + 20
H
11-2