Fifo Control Register (Ssifcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.5

FIFO Control Register (SSIFCR)

SSIFCR is a 32-bit readable/writable register that specifies the data trigger numbers for the transmit and receive FIFO
data registers, and enables or disables FIFO data resets and interrupt requests.
SSIFCR can always be read or written by the CPU.
Bit: 31
-
Initial value:
0
R/W:
R
Bit: 15
-
Initial value:
0
R/W: R
Bit Bit Name
31 to 8 ―
7, 6 TTRG[1:0]
5, 4 RTRG[1:0]
3 TIE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
00 R/W
00 R/W
0 R/W
25 24 23 22 21
- - - -
0 0 0 0
R R R R
9 8 7 6
- - TTRG[1:0]
0 0
0 0
R R R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Transmit Data Trigger Number
When the FIFO is operating for transmission, these bits specify the number
of bytes for transmission in the FIFO (trigger number for transmission) at
which the TDE flag in the FIFO status register (SSIFSR) will be set. The TDE
flag is set to 1 when the number of bytes for transmission in the transmit
FIFO data register (SSIFTDR) has fallen to or below the trigger number
corresponding to the setting as shown below.
00: 7 (1)*
01: 6 (2)*
10: 4 (4)*
11: 2 (6)*
Note: * The values in parentheses are the number of empty stages in
SSIFTDR at which the TDE flag is set.
Receive Data Trigger Number
When the FIFO is operating for reception, these bits specify the number of
received bytes in the FIFO (trigger number for reception) at which the RDF
flag in the FIFO status register (SSIFSR) will be set. The RDF flag is set to 1
when the number of received bytes in the receive FIFO data register
(SSIFRDR) has risen to or above the trigger number corresponding to the
setting as shown below.
00: 1
01: 2
10: 4
11: 6
Transmit Interrupt Enable
This bit enables or disables generation of transmit data empty interrupt (TXI)
requests in the following situation: when the FIFO is operating for
transmission, the data for transmission in the transmit FIFO data register
(SSIFTDR) are transferred to the transmit data register (SSITDR) and the
number of data bytes in the transmit FIFO data register has become less
than the set transmit trigger number, so that the TDE flag in the FIFO status
register (SSIFSR) is set to 1.
0: Transmit data empty interrupt (TXI) request is disabled.
1: Transmit data empty interrupt (TXI) request is enabled.*
Note: * TXI can be cleared by clearing either the TDE flag (see the
description of the TDE bit for details) or TIE bit to 0.
19. Serial Sound Interface
20 19 18 17
- - - - -
0 0 0 0 0
R R R R R
5 4 3 2 1
RTRG[1:0] TIE RIE TFRST
0 0 0 0 0
R/W R/W R/W R/W
16
-
0
R
0
RFRST
0
R/W
19-13