Access Wait Control - Renesas RZ/A Series User Manual

Hide thumbs Also See for RZ/A Series:

Table of Contents

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Access Wait Control

Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is

possible for areas 1, 4, and 5 to insert wait cycles independently in read access and in write access. Areas 0, 2, and 3 have

common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a

normal space access shown in Figure 8.8.

Wait Timing for Normal Space Access (Software Wait Only)

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

Note: * The waveform for DACKn is when active low is specified.

8. Bus State Controller

Rz/a1 series Rz/a1lu series Rz/a1lc series