Internal Clock Signals (2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.10.6

Internal Clock Signals (2)

Peripheral clock 1C
(P1φ max. 66.67 MHz)
Peripheral clock 0
(P0φ max. 33.33 MHz)
Peripheral clock 0C
(P0φ max. 33.33 MHz)
Figure 6.10 Distribution of Internal Clock Signals (2)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Module standby signals
Serial communication interface with FIFO, 5 channels
Serial communication interface, 2 channels
CAN interface, 2 channels
Internal bus (peripheral buses 3 and 4)
Interrupt controller
Direct memory access controller
Module standby signals
Realtime clock
2
I
Video display controller 5
Internal bus (peripheral buses 1 and 2)
Interrupt controller
Direct memory access controller
Watchdog timer
General input/output port
Module standby signals
OS timer, 2 channels
Multi-function timer pulse unit 2
IEBus
LIN interface (RZ/A1L only)
Internal buses (peripheral buses 1 and 2)
Interrupt controller
Direct memory access controller
C bus interface, 4 channels
TM
controller (RZ/A1L only)
6. Clock Pulse Generator
6-19