Dma Acknowledge Output Function - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.7.5

DMA Acknowledge Output Function

DACK0 is an acknowledge signal that is sent to DREQ0. Level output and bus cycle output settings are supported as the
DACK0 output mode. DACK0 is asserted at the same time as CS assertion except for the MPX-IO interface. For details,
refer to section 8, Bus State Controller.
(1) DMA Acknowledge Signal Output Timing Setting
Upon receiving a DMA transfer request, the DACK0 pin becomes active (High level output). By using the REQD and
AM[2:0] bits of the CHCFG_n register, the DACK0 output timing can be set as shown below.
Table 9.19 DACK0 Output Timing Setting
AM[2]
Mode (CHCFG_0)
Pulse 0
Level 0
Bus cycle 0
Mask 1
(2) Level Output
Setting 001 in the AM bits of the CHCFG_n register enables level output. DACK0 remains asserted until DREQ0 is
deasserted.
CKIO
CHCFG_n.AM[2:0]
CHCFG_n.REQD
DREQ0
Internal request
DACK0
DMA Transfer
Figure 9.19 DACK0 Output Timing (AM[2:0] = 001, REQD = 0)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
AM[1:0] REQD
(CHCFG_0) (CHCFG_0)
00 0
1
01 0 (Active during read)
1 (Active during write)
10 0 (Active during read)
11
1 (Active during write)
— —
9. Direct Memory Access Controller
Purpose
Setting prohibited
DACK0 is output as a level. DACK0
remains asserted until DREQ0 is
deasserted.
DACK0 is output for the duration of a bus
cycle. Use this mode when you want to
keep DACK0 asserted until the end of the
bus cycle.
Make this setting when using auto request
trigger.
001
Read Write
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