Usage Notes; Scftdr Writing And Tdfe Flag; Scfrdr Reading And Rdf Flag; Restriction On Direct Memory Controller Usage - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.6

Usage Notes

Note the following when using this module.
14.6.1

SCFTDR Writing and TDFE Flag

The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit
FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG[1:0] in the FIFO control
register (SCFCR). After the TDFE flag is set, transmit data up to the number of empty bytes in SCFTDR can be written,
allowing efficient continuous transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE
flag will be set to 1 again after being read as 1 and cleared to 0. The TDFE flag should therefore be cleared to 0 after
being read as 1 when SCFTDR contains more than the transmit trigger number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register
(SCFDR).
14.6.2

SCFRDR Reading and RDF Flag

The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data
register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG[1:0] in the FIFO
control register (SCFCR). After RDF flag is set, receive data equivalent to the trigger number can be read from
SCFRDR, allowing efficient continuous reception.
However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again after
being read as 1 and then cleared to 0. The RDF flag should therefore be cleared to 0 after being read as 1 after reading the
number of the received data in the receive FIFO data register (SCFRDR) which is less than the trigger number.
The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register
(SCFDR).
14.6.3

Restriction on Direct Memory Controller Usage

When the direct memory access controller writes data to SCFTDR due to a TXI interrupt request, the state of the TEND
flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag in such a case.
14.6.4

Break Detection and Processing

Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state
the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Note that, although transfer of receive data to SCFRDR is halted in the break state, the receive operation is continued.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14. Serial Communication Interface with FIFO
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