Slave Reception (Fifo Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
22.5.10

Slave reception (FIFO mode)

Table 22-55 Communication startup processing
Register name
IEBBnBCR
Start
IEBBTSTA
Note No start interrupt occurs.
IEBBTV
IEBBTD
Figure 22-42 Interrupt occurrence timing
Error occurrence judgment
Communication end
judgment
Frame end judgment
Figure 22-43 Reception completion interrupt (IEBBTV, IEBBTSTA) CPU processing
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
The unit receives data and commands from the master unit as a slave.
(1) Register settings
After specifying the initial settings in 22.5.2 Initial settings, set up the registers
below before starting communication.
Communication startup processing
(2) Interrupt occurrence timing
Broad
M address P Control
S address P A
cast
Note A data interrupt occurs at the timing specified by
(3) Interrupt servicing examples
(a) Reception completion interrupt (IEBBTV, IEBBTSTA) CPU processing flow
example
Error processing
Communication end
processing
Frame end processing
flow example
Function
Message
P A P A Data 1 P A
length
the IEBBnTMS.IEBBnSLTI1 and IEBBnSLTI0 bits.
Note
No data interrupt occurs.
Note
Determine if a message length worth of data could be received within
one frame by using frame end judgment. For example, if reception of
a message length worth of data has not finished, the subsequent
communications depend on the master processing.
22. IEBus Controller
Example
88H
... Data m P A ... Data n
Reception end
interrupt
Reception end
interrupt
P A
22-98