Address Match Detection; Slave-Address Match Detection - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.9

Address Match Detection

The RIIC can set three unique slave addresses in addition to the general call address and host address,
and also can set 7-bit or 10-bit slave addresses.
18.9.1

Slave-Address Match Detection

The RIIC can set three unique slave addresses, and has a slave address detection function for each
unique slave address. When the RIICnSER.SARy bit (y = 0 to 2) is set to 1, the slave addresses set in
RIICnSARy (y = 0 to 2) can be detected.
When the RIIC detects a match of the set slave address, the corresponding RIICnSR1.AASy flag (y = 0
to 2) is set to 1 at the rising edge of the ninth SCL clock cycle, and the RIICnSR2.RDRF flag or the
RIICnSR2.TDRE flag is set to 1 by the following R/W# bit. This causes a receive data full interrupt
(INTRIICRI) or transmit data empty interrupt (INTRIICTI) to be generated. The AASy flag is used to
identify which slave address has been specified.
Figure 18.24 to Figure 18.26 show the AASy flag set timing in three cases.
[7-bit address format: Slave reception]
SCLn
SDAn
BBSY
AASy
TRS
TDRE
RDRF
[7-bit address format: Slave transmission]
SCLn
SDAn
BBSY
AASy
TRS
TDRE
RDRF
Figure 18.24
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
S 1 2 3 4 5 6
7-bit slave address
S 1 2 3 4 5 6
7-bit slave address
AASy Flag Set Timing with 7-Bit Address Format Selected
7 8 9 1 2 3 4
Data (DATA 1)
ACK
W
Address match
Receive data (7-bit address)
Read RIICnDRR
(Dummy read [7-bit address])
7 8 9 1 2 3 4
Data (DATA 1)
R ACK
Address match
Transmit data (DATA 1)
Write data to RIICnDRT Write data to RIICnDRT
(DATA 2)
(DATA 1)
18. I²C Bus Interface
5 6 7 8 9 1 2
ACK
Receive data (DATA 1)
Read RIICnDRR
(DATA 1)
5 6 7 8 9 1 2
ACK
Transmit data (DATA 2)
Write data to RIICnDRT
(DATA 3)
3 4 5
Data (DATA 2)
3 4 5
Data (DATA 2)
18-67