Timer Dead Time Enable Register (Tder) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.28

Timer Dead Time Enable Register (TDER)

TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. This
module has one TDER in channel 3. TDER must be modified only while TCNT stops.
Bit Bit Name
7 to 1 —
0 TDER
Note: TDDR must be set to 1 or a larger value.
*
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
- -
Initial value: 0 0
R/W: R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
1 R/(W) Dead Time Enable
Specifies whether to generate dead time.
0: Does not generate dead time
1: Generates dead time*
[Clearing condition]
• When 0 is written to TDER after reading TDER = 1
5 4 3 2 1
- - - - -
0 0 0 0 0
R R R R R
10. Multi-Function Timer Pulse Unit 2
0
TDER
1
R/(W)
10-59