Riicnbrh - I²C Bus Bit Rate High-Level Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.13 RIICnBRH — I²C Bus Bit Rate High-Level Register
Access: RIICnBRH is a 32-bit readable/writable register.
RIICnBRHL and RIICnBRHH are 16-bit readable/writable registers.
RIICnBRHLL, RIICnBRHLH, RIICnBRHHL, and RIICnBRHHH are 8-bit readable/writable registers.
Address: RIICnBRH: <RIICn_base> + 0038
RIICnBRHL: <RIICn_base> + 0038
RIICnBRHLL: <RIICn_base> + 0038
RIICnBRHHH:<RIICn_base> + 003B
Initial Value: 0000 00FF
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.19
Bit Position
31 to 8
7 to 5
4 to 0
RIICnBRH is a 5-bit register to set the high-level period of SCL clock. RIICnBRH is valid in master
mode. If the RIIC is used only in slave mode, this register need not to set the high-level period.
RIICnBRH counts the high-level period with the internal reference clock source (IICφ) specified by the
RIICnMR1.CKS[2:0] bits.
The frequency and duty cycle are calculated using one of the following expressions (1) to (5) according
to the register settings.
CAUTION
The minimum value that can be specified in RIICnBRL and RIICnBRH is determined
according to the values of the SCLE and NFE bits in RIICnFER and the NF bit in RIICnMR3.
For details of the minimum specifiable value, see Table 18.20.
(1) When SCLE = 0
Frequency = 1 / {[ (BRH + 1) + (BRL + 1)] / IICφ + tr + tf}
Duty cycle = {tr + (BRH + 1) / IICφ} / {tr + tf + [(BRH + 1) + (BRL + 1)] / IICφ}
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnBRHH: <RIICn_base> + 003A
H
, RIICnBRHLH: <RIICn_base> + 0039
H
H
This register is initialized by any reset.
H
28 27 26 25
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnBRH register contents
Bit Name Function
― Reserved
These bits are read as 0. The write value should be 0.
— Reserved
These bits are read as 1. The write value should be 1.
BRH[4:0] Bit Rate High-Level Period
High-level period of SCL clock
H
, RIICnBRHHL: <RIICn_base> + 003A
H
24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — — —
0 0 1 1
R R R R
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
— BRH[4:0]
1 1 1 1
R R/W R/W R/W
,
H
17 16
— —
0 0
R R
1 0
1 1
R/W R/W
18-38