Receive Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.4.7

Receive Operation

Like transmission, reception can be controlled either by DMA transfer or interrupt.
Figure 19.25 and Figure 19.26 show the flow of operation.
When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit indicates that the module
is in the idle state.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.
(1) Reception Using Direct Memory Access Controller
Figure 19.25 Reception Using Direct Memory Access Controller
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Start
Release from reset,
set SSICR configuration bits.
Set up the direct memory
access controller.
Enable the direct memory
access controller.
Enable error interrupts
and receive interrupts,
then enable reception.
Wait for an interrupt.
Error interrupt?
No
No
End of DMA transfer?
Yes
Yes
More data to be received?
No
Disable receive operation,
disable an error interrupt,
enable an idle interrupt.
Wait for an idle interrupt
from this module
End*
Note: * If an error interrupt (underflow/overflow) occurs,
go back to the start in the flowchart again.
Define SCKD, SWSD, MUEN,
DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL,
CHNL
RUIEN = 1, ROIEN = 1, RIE = 1,
REN = 1
Yes
REN = 0,
RUIEN = 0, ROIEN = 0,
IIEN = 1, RIE = 0
19. Serial Sound Interface
19-36