Transmitter Channel 2 Status Register (Trcs) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.7.8

Transmitter Channel 2 Status Register (TRCS)

The 30-bit register stores the channel status information to be transmitted. For each channel, channel status information
per frame consists of 192 bits. Because necessary data covers only the 30 bits that are set in the following register, zeros
continue to be sent after the transmission of the first 30 bits.
Bit Bit Name
31, 30 ―
29, 28 CLAC[1:0]
27 to 24 FS[3:0]
23 to 20 CHNO[3:0]
19 to 16 SRCNO[3:0]
15 to 8 CATCD[7:0]
7, 6 ―
5 to 1 CTL[4:0]
0 ―
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 31 30 29
- - CLAC[1:0]
Initial value: - - 0
R/W: W W W
Bit: 23 22 21
CHNO[3:0]
Initial value: 0 0 0
R/W: W W W
15 14 13
Bit:
0 0 0
Initial value:
W W W
R/W:
7 6 5
Bit:
- -
0 0 0
Initial value:
W W W
R/W:
Initial
Value R/W Description
― W Reserved
All 0 W Clock Accuracy
00: Level 2
01: Level 1
10: Level 3
11: Reserved
All 0 W Sample Frequency (FS)
0000: 44.1 kHz
0010: 48 kHz
0011: 32 kHz
All 0 W Channel Number
0000: Don't care
0001: A (left channel)
0010: B (right channel)
0011: C
All 0 W Source Number
0000: Don't care
0001: 1
0010: 2
0011: 3
All 0 W Category Code (Example)
00000000: 2-channel general format
00000001: 2-channel compact disc (IEC 908)
00000010: 2-channel PCM encoder/decoder
00000011: 2-channel digital audio tape recorder
All 0 W Reserved
The write value should always be 0.
All 0 W Control
The control bits are copied from the source (see IEC60958 standard).
0 W Reserved
The write value should always be 0.
28 27 26 25 24
FS[3:0]
0 0 0 0 0
W W W W W
20 19 18 17 16
SRCNO[3:0]
0 0 0 0 0
W W W W W
12 11 10 9 8
CATCD[7:0]
0 0 0 0 0
W W W W W
4 3 2 1 0
CTL[4:0] -
0 0 0 0 0
W W W W W
23. Renesas SPDIF Interface
23-15