Spi Mode Read Data Register 0 (Smrdr0); Spi Mode Read Data Register 1 (Smrdr1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.14

SPI Mode Read Data Register 0 (SMRDR0)

SMRDR0 is a 32-bit register that stores the read data in SPI operating mode.
Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the
SPI mode enable setting register (SMENR). Be sure to access from address 0.
The settings of this register should be read when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
Initial value:
UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
R/W: R
Bit: 15
Initial value:
UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
R/W: R
Bit Bit Name
31 to 0 RDATA0
[31:0]
Note: The contents of this register and SMRDR1 are modified upon completion of reception in SPI operating mode. Be sure to read data
when reception in SPI operating mode is completed.
17.4.15

SPI Mode Read Data Register 1 (SMRDR1)

SMRDR1 is a 32-bit register that stores the read data in SPI operating mode.
This register is enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and
disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected).
Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the
SPI mode enable setting register (SMENR). Be sure to access from address 0.
The settings of this register should be read when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
Initial value:
UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
R/W:
R
Bit: 15
Initial value:
UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
R/W: R
Bit Bit Name
31 to 0 RDATA1
[31:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
R R R R R
14 13 12 11 10
R R R R R
Initial
Value R/W
Undefined R
30 29 28 27 26
R R R R R
14 13 12 11 10
R R R R R
Initial
Value R/W
Undefined R
25 24 23 22 21
RDATA0[31:16]
R R R R R
9 8 7 6 5
RDATA0[15:0]
R R R R R
Description
Read Data
Holds the data read in SPI operating mode.
Data bits differ depending on the settings of SFDE and BSZ[1:0] bits in
CMNCR and SPIDE[3:0] bits in SMENR.
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 1: Read data[63:32].
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 0: Read data[31:0].
Other than the above: Read data[31:0].
25 24 23 22 21
RDATA1[31:16]
R R R R R
9 8 7 6 5
RDATA1[15:0]
R R R R R
Description
Read Data
Holds the data read in SPI operating mode.
Data bits differ depending on the settings of SFDE and BSZ[1:0] bits in
CMNCR and SPIDE[3:0] bits in SMENR.
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 1: Read data[31:0].
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 0: Read data[63:32].
Other than the above: Bits in this register are disabled.
17. SPI Multi I/O Bus Controller
20 19 18 17 16
R R R R R
4 3 2 1 0
R R R R R
20 19 18 17 16
R R R R R
4 3 2 1 0
R R R R R
17-22