Rscan0Rfpctrx - Receive Fifo Buffer Pointer Control Register (X = 0 To 7) - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.25
RSCAN0RFPCTRx — Receive FIFO Buffer Pointer Control Register
(x = 0 to 7)
Access:
Can be written in 8-, 16-, and 32-bit units
Address:
<RSCAN0_base> + 00F8
Initial value:
0000 0000
Bit
31
30
29
Initial value
0
0
0
R/W
R
R
R
Bit
15
14
13
0
0
0
Initial value
R/W
R
R
R
Table 21.39
Bit Position
31 to 8
7 to 0
RFPC[7:0] Bits
When the RFPC[7:0] bits are set to FF
receive FIFO buffer. At this time, the RFMC[7:0] (receive FIFO unread message counter) value in the
RSCAN0RFSTSx register is decremented. Read the RSCAN0RFID, RSCAN0RFPTR,
RSCAN0RFDF0, and RSCAN0RFDF1 registers to read messages in the receive FIFO buffer, and then
write FF
Write FF
buffers are used) and the RFEMP flag in the RSCAN0RFSTSx register is 0 (the receive FIFO buffer
contains unread messages).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (x * 0004
)
H
H
H
28
27
26
0
0
0
R
R
R
12
11
10
0
0
0
R
R
R
RSCAN0RFPCTRx register contents
Bit Name
Function
Reserved
The write value should always be 0.
RFPC[7:0]
Receive FIFO Pointer Control
When these bits are set to FF
message in the receive FIFO buffer.
to the RFPC[7:0] bits.
H
to these bits when the RFE bit in the RSCAN0RFCCx register is set to 1 (receive FIFO
H
25
24
23
22
0
0
0
0
R
R
R
R
9
8
7
6
0
0
0
0
R
R
W
W
, the read pointer moves to the next unread
H
, the read pointer moves to the next unread message in the
H
21. CAN Interface
21
20
19
18
0
0
0
0
R
R
R
R
5
4
3
2
RFPC[7:0]
0
0
0
0
W
W
W
W
17
16
0
0
R
R
1
0
0
0
W
W
21-61

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