Sram Interface With Byte Selection - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
A25 to A0
RD/WR
D31 to D0
WAIT
DACKn*
Figure 8.33 Burst ROM Access Timing (Clocked Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer
(Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and
Subsequent Access Cycles = 1)
8.5.8

SRAM Interface with Byte Selection

The SRAM interface with byte selection is a memory interface that outputs the byte selection signal (WEn) in both read
and write bus cycles. This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins,
such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte
selection is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the
byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic
access timing is shown in Figure 8.34. In write access, data is written to the memory according to the timing of the byte-
selection pin (WEn). For details, refer to the Data Sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 8.35 shows the basic access
timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data
hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in CSnWCR.
Figure 8.36 shows the access timing when a software wait is specified.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
T1 Tw Tw
CKIO
CSn
RD
BS
Note: * The waveform for DACKn is when active low is specified.
T2B Twb T2B Twb T2B
8. Bus State Controller
Twb T2
8-78