Dma Extension Resource Selectors 0 To 7 (Dmars0 To Dmars7) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.25

DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7)

DMARS are 32-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each
channel. DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, and so on.
Table 9.4 shows the specifiable combinations.
DMARS can specify transfer requests to be accepted for the following triggers.
The following modules can issue on-chip peripheral module requests.
Serial communication interface with FIFO: 10 sources
A/D converter: 1 source
Multi-function timer pulse unit 2: 5 sources
USB2.0 host/function module: 4 sources
Serial sound interface: 7 sources
Renesas SPDIF interface: 2 sources
CD-ROM decoder: 1 source (RZ/A1L only)
SD host interface: 4 sources
MMC host interface: 2 sources
Renesas serial peripheral interface: 6 sources
IEBus™ controller: 2 sources (RZ/A1L only)
OS timer: 2 sources
SCUX: 8 sources
Media local bus: 1 source (RZ/A1L only)
Serial communication interface: 4 sources
2
I C bus interface: 8 sources
LIN interface: 2 sources (RZ/A1L only)
Some on-chip peripheral modules in this product use the same signal both for an interrupt request and for a DMA transfer
request. If such a module is selected by a DMARS register, the signal works as a DMA transfer request signal and
interrupt requests to the interrupt controller are masked. To enable the interrupt, clear the setting of DMARS (set all
MID[6:0] and RID[1:0] to 0).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
9. Direct Memory Access Controller
9-31