Cascaded Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0
to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.42 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates
independently in phase counting mode.
Table 10.42 Cascaded Combinations
Combination
Channels 1 and 2
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins
can be specified by the input capture control register (TICCR). The condition for input capture is the detection of an edge
in the signal obtained from the logical OR of the signal on the main input pin and the signal on the additional input pin.
For details, see (4), Cascaded Operation Example (c). For input capture in cascade connection, refer to section 10.7.22,
Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection.
Table 10.43 show the TICCR setting and input capture input pins.
Table 10.43 TICCR Setting and Input Capture Input Pins
Target Input Capture
Input capture from TCNT_1 to TGRA_1
Input capture from TCNT_1 to TGRB_1
Input capture from TCNT_2 to TGRA_2
Input capture from TCNT_2 to TGRB_2
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Upper 16 Bits
TCNT_1
TICCR Setting
I2AE bit = 0 (initial value)
I2AE bit = 1
I2BE bit = 0 (initial value)
I2BE bit = 1
I1AE bit = 0 (initial value)
I1AE bit = 1
I1BE bit = 0 (initial value)
I1BE bit = 1
10. Multi-Function Timer Pulse Unit 2
Lower 16 Bits
TCNT_2
Input Capture Input Pins
TIOC1A
TIOC1A, TIOC2A
TIOC1B
TIOC1B, TIOC2B
TIOC2A
TIOC2A, TIOC1A
TIOC2B
TIOC2B, TIOC1B
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