Watchdog Reset Control/Status Register (Wrcsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
12.3.3

Watchdog Reset Control/Status Register (WRCSR)

WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog
timer counter (WTCNT) overflow.
Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section
12.3.4, Notes on Register Access for details.
Bit Bit Name
7 WOVF
6 RSTE
—
5
—
4 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
WOVF RSTE
Initial value: 0 0
R/W: R/(W) R/W
Initial
Value R/W Description
0 R/(W) Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is
not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
• When 0 is written to WOVF after reading WOVF
0 R/W Reset Enable
Selects whether to generate a signal to reset the LSI internally if WTCNT
overflows in watchdog timer mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and WTCSR reset within this
0 R Reserved
This bit is always read as 0. The write value should always be 0.
All 1 R Reserved
These bits are always read as 1. The write value should always be 1.
5 4 3 2 1
- - - - -
0 1 1 1 1
R R R R R
module.
12. Watchdog Timer
0
-
1
R
12-5