Rscan0Gaflidj - Receive Rule Id Register (J = 0 To 15) - Renesas RZ/A Series User Manual

Hide thumbs Also See for RZ/A Series:
Table of Contents

Advertisement

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.13
RSCAN0GAFLIDj — Receive Rule ID Register (j = 0 to 15)
Access:
Can be read/written in 8-, 16-, and 32-bit units
Address:
<RSCAN0_base> + 0500
Initial value:
0000 0000
Bit
31
30
29
GAFLID
GAFLR
GAFLLB
E
TR
Initial value
0
0
0
R/W
R/W
R/W
R/W
Bit
15
14
13
0
0
0
Initial value
R/W
R/W
R/W
R/W
Table 21.27
Bit Position
b31
b30
b29
b28 to b0
Modify the RSCAN0GAFLIDj register when the AFLDAE bit in the RSCAN0GAFLECTR register is
set to 1 (receive rule table write is enabled) in global reset mode.
GAFLIDE Bit
This bit is used to select the ID format (standard ID or extended ID) of the receive rule. This bit is
compared with the IDE bit in the received message during the acceptance filter processing.
GAFLRTR Bit
This bit is used to select the frame format (data frame or remote frame) of the receive rule. This bit is
compared with the RTR bit in the received message during the acceptance filter processing.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (j * 0010
)
H
H
H
28
27
26
0
0
0
R/W
R/W
R/W
12
11
10
0
0
0
R/W
R/W
R/W
RSCAN0GAFLIDj register contents
Bit Name
Function
GAFLIDE
IDE Select
GAFLRTR
RTR Select
GAFLLB
Receive Rule Target Message Select
GAFLID[28:0]
ID
Set the ID of the receive rule.
For the standard ID, set the ID in bits b10 to b0 and set bits b28 to b11 to 0.
25
24
23
22
GAFLID[28:16]
0
0
0
0
R/W
R/W
R/W
R/W
9
8
7
6
GAFLID[15:0]
0
0
0
0
R/W
R/W
R/W
R/W
0: Standard ID
1: Extended ID
0: Data frame
1: Remote frame
0: When a message transmitted from another CAN node is received
1: When the own transmitted message is received
21. CAN Interface
21
20
19
18
0
0
0
0
R/W
R/W
R/W
R/W
5
4
3
2
0
0
0
0
R/W
R/W
R/W
R/W
17
16
0
0
R/W
R/W
1
0
0
0
R/W
R/W
21-45

Advertisement

Table of Contents
loading

This manual is also suitable for:

Rz/a1 seriesRz/a1lu seriesRz/a1lc series

Table of Contents