Operation; Initial Settings - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
7.6

Operation

7.6.1

Initial Settings

For details on the registers for making initial settings and the procedures for settings in general, see the Arm Generic
Interrupt Controller Architecture Specification and the PrimeCell
Reference Manual from Arm. Figure 7.2 illustrates the flow of initial settings.
Figure 7.2 Flow of Initial Settings
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Start initial settings
GIC interrupt request acknowledgement initial setting 1
(1) ICDISRn Interrupt security register
For ICDISR0 to ICDISR16, set H'00000000.
(2) ICDICFRn Interrupt configuration register
Set ICDICFR0 to ICDICFR33 to the values in table 7.4.
Set ICDICFR26 to ICDICFR33 to the mode for detecting pin interrupts.
(3) ICDIPRn Interrupt priority register
Set the priority levels for interrupts with the corresponding IDs in the fields
of ICDIPR0 to ICDIPR134.
(4) ICDIPTRn Target CPU setting
Set the value H'01 for interrupts with the corresponding IDs in the fields of
ICDIPTR8 to ICDIPTR134. (ICDIPTR0 to ICDIPTR7 are read-only.)
(5) ICDISERn Interrupt set-enable register
For interrupts which are to be enabled, set the corresponding bits of
ICDISER0 to ICDISER16 to 1.
CPU interface initial setting
(1) ICCPMR Interrupt priority mask register
Specify the priority level at and above which the CPU will be notified.
(2) ICCBPR Binary point register
Set the separation point for the fractional part of the priority value field.
(3) ICCICR CPU interface control register
Set this register to H'00000003.
GIC interrupt request acknowledgement initial setting 2
(1) ICDDCR Distributor control register
Set the enable bit to 1.
CPU initial setting
(1) CSPR
Clear the I and F bits to 0.
Initial settings
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Generic Interrupt Controller (PL390) Technical
completed
7. Interrupt Controller
7-36