Data Read Control Register (Drcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.4

Data Read Control Register (DRCR)

DRCR is a 32-bit register that sets the operation in external address space read mode.
The bits except the SSLN bit should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value:
0
R/W:
R
Bit Bit Name
31 to 25 ―
24 SSLN
23 to 20 ―
19 to 16 RBURST
[3:0]
15 to 10 ―
9 RCF
8 RBE
7 to 1 ―
0 SSLE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 W
All 0 R
0000 R/W
All 0 R
0 W
0 R/W
All 0 R
0 R/W
25 24 23 22 21
- SSLN - - -
0 0 0 0 0
R W R R R
9 8 7 6 5
RCF RBE - - -
0 0 0 0 0
W R/W R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
SPBSSL Negation
Asserted SPBSSL can be negated by writing 1 to this bit when both the
RBE and SSLE bits are 1.
This bit is always read as 0.
Note: To start next access after SPBSSL negation using this bit, read
SSLF in CMNSR = 0 to confirm that the SPBSSL has been
negated.
Reserved
These bits are always read as 0. The write value should always be 0.
Read Data Burst Length
Sets the burst length (data unit count) when reading.
This bit is enabled when the RBE bit is set to 1.
0000: 1 data unit
0001: 2 continuous data units
:
1110: 15 continuous data units
1111: 16 continuous data units
One data unit is 64 bits long.
Reserved
These bits are always read as 0. The write value should always be 0.
Read Cache Flush
When 1 is written to this bit, all the entries in the read cache are cleared.
This bit is always read as 0.
Note: After flushing the read cache by writing 1 to the RCF bit, read the
DRCR before proceeding to read from the external address space.
Read Burst
Turns burst ON or OFF when reading.
0: Data is read according to the access size.
1: Read cache is enabled, and as many data units as the burst count
specified in RBURST[3:0] bits is read.
Reserved
These bits are always read as 0. The write value should always be 0.
SPBSSL Negation
Sets the conditions for SPBSSL negation during read burst.
SPBSSL is negated for each access during normal read.
0: SPBSSL is negated after transfer of data set in burst length.
1: SPBSSL is negated when the accessed address is not continuous with
the previously transferred address.
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- RBURST[3:0]
0 0 0 0 0
R R/W R/W R/W R/W
4 3 2 1 0
- - - - SSLE
0 0 0 0 0
R R R R R/W
17-11