Serial Communication Interface With Fifo; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.

Serial Communication Interface with FIFO

This LSI has a five-channel serial communication interface with FIFO that supports both asynchronous and clock
synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently
for each channel that enable this LSI to perform efficient high-speed continuous communication.
14.1

Features

• Asynchronous serial communication:
—
Serial data communication is performed by start-stop in character units. This module can communicate with a
universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter
(ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight
selectable serial data communication formats.
—
Data length: 7 or 8 bits
—
Stop bit length: 1 or 2 bits
—
Parity: Even, odd, or none
—
Receive error detection: Parity, framing, and overrun errors
—
Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level
(low level). It is also detected by reading the RxD pin level directly from the serial port register when a framing
error occurs.
• Clock synchronous serial communication:
—
Serial data communication is synchronized with a clock signal. This module can communicate with other chips
having a clock synchronous communication function. There is one serial data communication format.
—
Data length: 8 bits
—
Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so this module can transmit
and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is
possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external)
• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-data-full interrupt, and
receive-error interrupt are requested independently.
• When this module is not in use, it can be stopped by halting the clock supplied to it, saving power.
• In asynchronous mode, on-chip modem control functions (RTS and CTS) (only channels 0, 1, and 2).
• The quantity of data in the transmit and receive FIFO data registers and the number of receive errors of the receive
data in the receive FIFO data register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
• In asynchronous mode, the base clock frequency can be either 16 or 8 times the bit rate.
• When an internal clock is selected as a clock source and the SCK pin is used as an input pin in asynchronous mode,
either normal mode or double-speed mode can be selected for the baud rate generator.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14. Serial Communication Interface with FIFO
14-1