Timer A/D Converter Start Request Cycle Set Registers (Tadcora_4 And Tadcorb_4); Timer A/D Converter Start Request Cycle Set Buffer Registers (Tadcobra_4 And Tadcobrb_4); Timer Counter (Tcnt) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.9 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)
TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in
TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued.
TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Bit: 15
Initial value: 1
R/W: R/W
Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
10.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4)
TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4
count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively.
TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Bit: 15
Initial value:
1
R/W: R/W
Note: TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
10.3.11

Timer Counter (TCNT)

The TCNT counters are 16-bit readable/writable counters. This module has five TCNT counters, one each for channels 0
to 4.
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
Bit: 15
Initial value: 0
R/W: R/W
Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
1 1 1 1 1
R/W R/W R/W R/W R/W
14 13 12 11 10
1 1 1 1 1
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
1 1 1 1 1
R/W R/W R/W R/W R/W
9 8 7 6 5
1 1 1 1 1
R/W R/W R/W R/W R/W
9 8 7 6 5
0 0 0 0 0
R/W R/W R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
4 3 2 1 0
1 1 1 1 1
R/W R/W R/W R/W R/W
4 3 2 1 0
1 1 1 1 1
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
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